Teaching Scheme : Lectures: 4 Hrs/Week

Examination Scheme: Theory: 100 Marks Duration : 3 Hrs

1. Algebra of logical variables

Review of Boolean algebraic theorems, realization of Boolean functions

and sufficiency of NAND/NOR for implementation, standard SOP and

POS forms of logical functions, minimization techniques using K - MAP

and Quine Mc Cluskey method (upto 4 variables). 6 hrs.

2. Logic Families

Basic TTL NAND with totem pole o/p and open collector o/p, Tristate

o/p, 1/0 parameters, fanin and fanout, Noise margin, propagation

delay, power dissipation etc. STTL, LSTTL, CMOS inverter, CMOS

NAND/NOR, CMOS characteristic CHMOS comparison of different

logic families, interfacing TTL to CMOS and vice versa. 6 hrs.

3. Design of combinational logic circuits :

Half adders/subtractors, Full - adder/subtractor, unsigned and signed

number representation, n-bit parallel adder/,5ub. with looi(-ahead carry,

BCD adder/sub using 7483, 74181 ALU; Code converter-bina@CD,

Excess-3, Gnay, Parity generator and checker, MUX, DEMUX,

encoders, implementation of Boolean functions using MUX, DEMUX,

BCD to 7-segment decoder-driver. 6 hrs.

4. Flip flops, Registers, Counters:

One bit Latch using NORINAND, steered latches, S-R FF, clocked S-R

FF, J-K FF, Race around condition, M/S J-K FF, D FF, T FF; shift registers-

SISO, SIPO, PIPO, PISO, applications of shift registers; Ripple Counters,

Synchronous counters of arbitrary modulo, UP/DOWN Counters,

Counter ICs like 7490, 7492, 7493, 74161, 74191, Functional block

diagram of frequency counter. 8 hrs.

5. Memories :

Random access memory, TrL RAM Cell, parameters, read/write cycles,

ROMs-types, EP.ROM structure and programming, MOS static RAM

Cell, Dynamic RAM Cell, refreshing, memory cycles. 4 hrs

6. Sequential circuits : '

Block diagrams, state variables and excitation variables, state diagram

representation, Moore and Mealy circuits, Design of sequence

generator and sequence detector, elimination of redundant states,

Avoiding lockouts, fundamental mode sequential circuits, elimination

critical races, hazards, pulse mode sequential circuits, Clock Circuits 8 hrs.

7. Moore & Mealy machines :

ASM harts, notations, design controller, Multiplexer

Controller method, RTL notations and implementation. 6 hrs

8. Programmable Logic Devices:

Programmable Logic elements and array logic, implementation of

combinational and sequential logic design using PLES, 5 hrs

introduction to PLD PLA's

1. Digital circuits and systems - Douglas Hall, MGH.

2. Digital Logic Degign - Morris Mano, PHI.